🧠 About • 🏗️ Datapath • 🔩 Components • 🚀 Quick Start • 🌊 GTKWave • 🌀 Fibonacci

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✨ Overview

Krypton-Core is a single-cycle RV32I RISC-V processor designed and implemented in Scala + Chisel.

It brings together a full processor datapath: instruction memory, register file, ALU, control logic, data memory, branch handling and next-PC generation. Every run can be dumped to a VCD and inspected cycle by cycle in GTKWave.

⚡ ISA          →  RV32I (RISC-V 32-bit base integer)
🧬 Design Style →  Single-cycle, one instruction per clock
🛠️ Language     →  Scala + Chisel (hardware construction)
🧪 Verification →  ChiselTest + GTKWave waveforms

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🧠 About Krypton-Core

Krypton-Core is a single-cycle RISC-V processor: every instruction travels through the whole datapath within one clock cycle.

The core follows the classic RISC-V execution flow:

Fetch → Decode → Execute → Memory → Write Back → Next PC

Because the whole design is written in Chisel, the hardware is describable, testable, and ready for RTL generation.

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🎯 Highlights

	Feature
🧩	Modular design: every block (ALU, RegFile, Controller...) is its own Chisel module
⏱️	Single-cycle execution: simple, easy-to-follow datapath
🔀	Branch + Jump support: branch logic and JAL/JALR handling
📝	Swappable programs: load different instruction files into instruction memory
🌊	Waveform debugging: generate VCDs and step through every clock cycle
🧪	Testable: run hardware tests straight from SBT

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🏗️ RISC-V Single-Cycle Datapath

The datapath connects the major processor components to execute RISC-V instructions.

Core Flow

            ┌─────────────┐
            │     PC      │
            └──────┬──────┘
                   ↓
         ┌──────────────────┐
         │ Instruction Mem  │
         └────────┬─────────┘
                  ↓
         ┌──────────────────┐
         │     Decode       │
         └────────┬─────────┘
                  ↓
      ┌───────────┴───────────┐
      ↓                       ↓
┌─────────────┐       ┌──────────────┐
│ Register    │       │ Immediate    │
│ File        │       │ Generator    │
└──────┬──────┘       └──────┬───────┘
       └──────────┬───────────┘
                  ↓
            ┌──────────┐
            │   ALU    │
            └────┬─────┘
                 ↓
       ┌─────────┴─────────┐
       ↓                   ↓
┌─────────────┐      ┌─────────────┐
│ Data Memory │      │   Next PC   │
└──────┬──────┘      └──────┬──────┘
       └──────────┬─────────┘
                  ↓
           ┌────────────┐
           │ Write Back │
           └────────────┘

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🔩 Processor Components

Component	Responsibility
🧭 Program Counter	Holds the current instruction address
📖 Instruction Memory	Fetches instructions
🧩 Instruction Decoder	Identifies the instruction type
🎛️ Controller	Generates processor control signals
🗃️ Register File	Reads and writes RISC-V registers
🔢 Immediate Generator	Generates instruction immediates
⚙️ ALU Control	Selects the required ALU operation
🧮 ALU	Performs arithmetic and logical operations
💾 Data Memory	Handles load/store operations
🔀 Branch Logic	Determines branch conditions
🏃 JAL/JALR Logic	Handles jump instructions
➡️ Next-PC Logic	Determines the next instruction address

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📂 Repository Structure

Click to expand the project tree

Krypton-Core/
│
├── 📁 images/                  # Banner, datapath diagram, GIF
├── 📁 project/                 # SBT project configuration
├── 📁 src/
│   ├── main/scala/core/
│   │   ├── ALU.scala
│   │   ├── InstMem.scala
│   │   ├── Top.scala
│   │   ├── RegFile.scala
│   │   ├── DataMem.scala
│   │   ├── Controller.scala
│   │   ├── Imm_gen.scala
│   │   └── ...
│   └── test/scala/core/        # ChiselTest testbenches
├── 📁 target/
├── 📁 test_run_dir/            # Generated test + VCD files
│
├── 📄 Assembly instructions.txt
├── 📄 fibonaciAssembly.txt
├── 📄 instruction.txt
├── 📄 build.sbt
├── 📄 LICENSE
└── 📄 README.md

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📝 Instruction Programs

Krypton-Core loads different instruction programs through the Instruction Memory.

File	What it contains
📘 Assembly instructions.txt	Assembly instructions for the main program
🌀 fibonaciAssembly.txt	Assembly implementation of the Fibonacci program
🔢 instruction.txt	Instruction data used by the processor

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🔄 Selecting a Program

The program executed by Krypton-Core is selected in InstMem.scala and Top.scala.

1️⃣ Configure Instruction Memory

Open src/main/scala/core/InstMem.scala and find:

class InstMem(initFile: String = "fibonaciAssembly.txt") extends Module with Config4

Change the filename to the program you want to run:

// Fibonacci
class InstMem(initFile: String = "fibonaciAssembly.txt") extends Module with Config4

// Main assembly program
class InstMem(initFile: String = "Assembly instructions.txt") extends Module with Config4

2️⃣ Configure the Top Module

Open src/main/scala/core/Top.scala and find:

class Top(initFile: String = "fibonaciAssembly.txt") extends Module

Change the filename to match the selected program:

class Top(initFile: String = "Assembly instructions.txt") extends Module

💡 Tip: Use the same filename in both files so the program stays consistent.

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⚡ Quick Start

# 1. Clone
git clone https://github.com/Blue-Rangoon/Krypton-Core.git

# 2. Enter the project
cd Krypton-Core

# 3. Start SBT
sbt

Inside SBT:

# 4. Run the processor test
testOnly core.TopTest

# 5. Run it and generate a waveform
testOnly core.TopTest -- -DwriteVcd=1

Then open the waveform:

gtkwave <generated-vcd-file>

You should see the SBT prompt, for example sbt:RISCV_Project>

The general test format is:

testOnly core.<TestName>

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🌊 GTKWave

The important option for waveform generation is:

-DwriteVcd=1

After the test finishes, open test_run_dir/, find the directory generated for the test, and open the VCD inside it:

gtkwave TopTest.vcd

🔬 What Can Be Observed?

GTKWave lets you inspect the processor cycle by cycle.

⏱ Clock          📍 PC             📖 Instruction
🧮 ALU            🗃 Register File   💾 Data Memory
🎛 Control Signals 🔀 Branch Signals  ➡ Next PC
📤 Register Output

Follow the whole execution by stepping through the clock cycles:

Clock Cycle 1  →  Instruction 1
Clock Cycle 2  →  Instruction 2
Clock Cycle 3  →  Instruction 3
        ...
Clock Cycle N  →  Instruction N

This gives a hardware-level view of how the RISC-V processor executes a program.

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🌀 Fibonacci Demonstration

One of the programs shipped with Krypton-Core is a Fibonacci implementation, stored in fibonaciAssembly.txt.

Run it in 4 steps:

1. Set fibonaciAssembly.txt in both InstMem.scala and Top.scala
2. Start SBT with sbt
3. Run testOnly core.TopTest (or add -- -DwriteVcd=1 for a waveform)
4. Inspect the generated VCD in GTKWave

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🧪 Verification Workflow

flowchart LR
    A[Select Program] --> B[Update InstMem.scala]
    B --> C[Update Top.scala]
    C --> D[sbt]
    D --> E[testOnly core.TopTest]
    E --> F[Generate VCD]
    F --> G[test_run_dir]
    G --> H[GTKWave]

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🛠️ Technologies

Technology	Used For
🟠 Chisel	Hardware Construction
🔴 Scala	Hardware Description
🟢 RISC-V RV32I	Instruction Set Architecture
🔵 SBT	Build & Testing
🟣 ChiselTest	Hardware Verification
🌊 GTKWave	Waveform Analysis

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🎯 Project Goals

Krypton-Core was built to explore the design and implementation of a RISC-V processor at the hardware level.

• 🧠 Understand the RISC-V architecture
• ⚙️ Design a single-cycle datapath
• 🔧 Implement processor components in Chisel
• 🧩 Connect datapath and control logic
• 🧪 Test hardware modules
• 📊 Generate VCD waveforms
• 🌊 Debug processor execution with GTKWave

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📚 RISC-V

Krypton-Core is based on the RISC-V RV32I instruction-set architecture, built around these fundamentals:

Registers + ALU + Memory + Control + Program Counter
                       ↓
              Instruction Execution

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🤝 Connect

Built by Blue Rangoon

A clean and simple single-cycle RV32I processor implemented in Chisel.

⭐ If you find this project useful, consider giving the repository a star!