Open hardware, from algorithms to RTL.
OpenETH provides reusable components for connecting a system-on-chip (SoC) to a Gigabit Ethernet PHY: a network controller and DMA, frame buffering and clock-domain crossing, MAC and CRC, RGMII I/O, and PHY management. The repository includes their Chisel and SystemVerilog sources, a Linux driver, bare-metal and Linux test programs, and simulation tests.
Release v1.1.0 · Interfaces · Build and test
- Network controller and DMA (OpenNIC): Chisel and generated RTL.
- Frame buffering and clock-domain crossing: sources and tests.
- MAC and CRC: sources and tests.
- RGMII and FPGA I/O: sources and tests.
- PHY management: MDIO integration and PHY utility.
- Datapath integration: RTL connections between components.
- Digital SoC integration: a pinned public Chipyard baseline, system configuration, bus/interrupt bindings and complete SV generation. See Chipyard SoC integration.
- Software: bare-metal native-stream loopback, Linux driver, PHY utility, and TCP integrity tests with a peer program.
- Integration contracts: packet streams, memory interfaces, register layout and reset behavior. See Interfaces for details.
Simulation covers NIC registers/DMA, MAC framing and CRC, frame-buffer clock crossing, and RGMII functional behavior, including backpressure, reset and intentional-error controls. Host-only C tests are listed separately; they are not RTL simulation. See Simulation verification for coverage and Build and test for commands and dependencies.
The VU13P FPGA reference system has been exercised with bare-metal packet/DMA tests and Linux driver, integrity and throughput tests. Functional correctness and zero-loss performance are separate conclusions. See Board validation for results and limits, and Reference hardware and connections for the setup.
Bare-metal: the supplied program checks the network controller through direct packet-stream loopback, without Linux or an external PHY path. See Bare-metal program for its platform requirements and pass criteria.
Linux: the repository provides the platform driver, PHY configuration utility and bidirectional TCP byte-integrity test. See Linux programs and Driver build and selection for details.
On the 50 MHz Rocket reference system, measured Linux TCP throughput is 27.089 Mbit/s RX, 25.235 Mbit/s TX, and 24.748 Mbit/s simultaneous RX+TX. RX/TX are relative to the FPGA; these are application measurements, not the PHY's 1-Gbit/s line rate, and UDP loss remains. See Performance test method and results for wiring, prerequisites, all 13 test cases, exact commands and statistics.
Component and digital SoC SV generation, simulation and software source builds are documented. The reference board system is described, but complete board projects, schematics, pin constraints, vendor-IP configurations and board boot images are not supplied. See Build and test, SoC integration and Reference system scope for details.
Original code uses the MIT License, permitting commercial use without purchasing services; preserve the third-party notices. For optional datapath customization or ASIC/FPGA integration, visit OpenRTL Lab.