librelane

ASIC implementation flow infrastructure, successor to OpenLane

A novel Design-for-Test flow using LibreLane

A Customized ASIC framework for Retro Stuff

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

KianV GF180 ASIC runs ulinux, linux and XV6

Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.

BLogic MCU - RISC-V (CV32E40P, RV32IMC) microcontroller SoC with a custom AXI4 interconnect and a TinyConv keyword-spotting AI accelerator (21× vs software). sky130 GDSII signed off at 27 MHz, runs on a Genesys 2 FPGA at 50 MHz, JTAG debug. TEKNOFEST 2026 Chip Design Competition - OSTİM Technical University

FazyRV Hachure is a System on Chip that integrates seven different variants of the bit-serial FazyRV RISC-V core in one chip for testing and research purposes.

Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation

VHDL 8-bit synchronous counter on SKY130: verified core RTL-to-GDS flow and an educational I/O pad-ring experiment.

AI/LLM-assisted circuit design using opensource tools

Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.

Chipathon 2026 workshop padring fork of wafer-space/gf180mcu-project-template - adds a workshop slot mirroring JuanMoya/padring_gf180 as a native LibreLane slot.

ASIC Design Flow of Signed 8x8 Booth-Wallace Multiplier (Radix-4)

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

Parameterized 32-bit ASIC ALU taken from RTL through synthesis, technology mapping, physical design, signoff, and GDSII generation using SKY130A. Includes multi-generation RTL history, 64-bit scaling experiments, verification, synthesis, and physical-design results.

Simple Systolic array implementation

Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.

From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.

Write Verilog. Prove it Works. Get a Chip Layout.