simplex-micro / riscv-vector-primer Star 149 Code Issues Pull requests Discussions Read chapters directly from this repo - do not use GitHub Pages link. open-hardware riscv computer-architecture instruction-set-architecture risc-v embedded-ai edge-ai rvv riscv-vector vector-processing matrix-acceleration Updated Jul 25, 2026
OpenRTL-Lab / prime-field-vector-goldilocks Star 0 Code Issues Pull requests MIT-licensed Goldilocks finite-field vector arithmetic and dot-product hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 素域向量运算与点积硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。 chisel rtl modular-arithmetic systemverilog hardware-acceleration zero-knowledge goldilocks finite-field vector-processing openrtl Updated Oct 17, 2026 SystemVerilog
MuhammadTahaBinZaeem / CS-117-Project Star 0 Code Issues Pull requests Single-cycle 20-bit Verilog CPU with scalar and vector operations, Harvard architecture, tests, and design documentation. verilog course-project computer-architecture cpu-architecture hardware-design vector-processing Updated Jan 15, 2026 Verilog
OpenRTL-Lab / extension-field-vector-goldilocks Star 0 Code Issues Pull requests MIT-licensed Goldilocks quadratic-extension vector arithmetic hardware accelerator. Chisel source and generated SystemVerilog. | MIT 开源 Goldilocks 二次扩域向量运算硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。 chisel rtl systemverilog hardware-acceleration zero-knowledge goldilocks finite-field vector-processing openrtl extension-field Updated Oct 17, 2026 SystemVerilog